Semiconductor device and method of manufacturing the same

ABSTRACT

In one embodiment, a method of manufacturing a semiconductor device includes sequentially forming a first insulator, a second insulator, and a sacrificial layer on a semiconductor substrate, and forming plural core materials from the sacrificial layer and the second insulator. The method further includes forming first and second interconnects on side surfaces of each core material to form plural first interconnects and plural second interconnects alternately, each first interconnect having a first side surface in contact with a core material and a second side surface positioned on an opposite side of the first side surface, and each second interconnect having a third side surface in contact with a core material and a fourth side surface positioned on an opposite side of the third side surface. The method further includes removing the sacrificial layer so that the second insulator remains, after the first and second interconnects are formed.

CROSS REFERENCE TO RELATED APPLICATION

This application is a division of and claims the benefit of priorityunder 35 U.S.C. §120 from U.S. Ser. No. 13/570,436 filed Aug. 9, 2012,and claims the benefit of priority under 35 U.S.C. §119 from JapanesePatent Application No. 2011-248750 filed Nov. 14, 2011, the entirecontents of each of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to a semiconductor device and amethod of manufacturing the same.

BACKGROUND

In recent years, sidewall interconnects have been studied to form fineinterconnects exceeding the limit of lithography. For example, thesidewall interconnects are formed on both sidewalls of a core materialwhich is formed of insulator. In this case, it is considered to reducethe capacitance between the sidewall interconnects by removing the corematerial after the sidewall interconnects are formed and forming aninsulator with a low permittivity or an air gap between the sidewallinterconnects. However, when the core material is removed, there is ahigh probability that the sidewall interconnects fall down. Therefore, atechnique which can achieve reduction in capacitance between theinterconnects while preventing falling of the interconnects is needed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view showing a structure of a semiconductordevice of a first embodiment;

FIGS. 2 and 3 are cross sectional views showing structures ofsemiconductor devices of modifications of the first embodiment;

FIGS. 4A to 6B are cross sectional views showing a method ofmanufacturing a semiconductor device of the first embodiment;

FIGS. 7A and 7B are cross sectional views showing a method ofmanufacturing a semiconductor device of a modification of the firstembodiment;

FIG. 8 is a cross sectional view showing a structure of a semiconductordevice of a second embodiment;

FIG. 9 is a cross sectional view showing a structure of a semiconductordevice of a modification of the second embodiment;

FIG. 10 is a cross sectional view showing a structure of a semiconductordevice of a third embodiment; and

FIG. 11 is a cross sectional view showing a structure of a semiconductordevice of a modification of the third embodiment.

DETAILED DESCRIPTION

Embodiments will now be explained with reference to the accompanyingdrawings.

In one embodiment, a method of manufacturing a semiconductor deviceincludes sequentially forming a first insulator, a second insulator, anda sacrificial layer on a semiconductor substrate, and forming aplurality of core materials from the sacrificial layer and the secondinsulator. The method further includes forming first and secondinterconnects on side surfaces of each core material to form a pluralityof first interconnects and a plurality of second interconnectsalternately on the first insulator, each first interconnect having afirst side surface in contact with a core material and a second sidesurface positioned on an opposite side of the first side surface, andeach second interconnect having a third side surface in contact with acore material and a fourth side surface positioned on an opposite sideof the third side surface. The method further includes removing thesacrificial layer so that the second insulator remains, after the firstand second interconnects are formed.

First Embodiment

FIG. 1 is a cross sectional view showing a structure of a semiconductordevice of a first embodiment.

The device in FIG. 1 includes a semiconductor substrate 1, a firstinsulator 2, sidewall interconnects 3, second insulators 4, air gaps 5,and a third insulator 6.

The semiconductor substrate 1 is, for example, a silicon substrate. FIG.1 shows directions X and Y which are parallel to a principal surface ofthe semiconductor substrate 1 and are perpendicular to each other, and adirection Z which is perpendicular to the principal surface of thesemiconductor substrate 1.

The first insulator 2 is formed on the semiconductor substrate 1. Thefirst insulator 2 is, for example, an inter layer dielectric. The firstinsulator 2 may be formed directly on the semiconductor substrate 1 ormay be formed on the semiconductor substrate 1 via another layer.Examples of the first insulator 2 include a silicon nitride (SiN) layer,a silicon oxide (SiO₂) layer, a silicon oxycarbide (SiOC) layer and thelike.

The sidewall interconnects 3 are formed on the first insulator 2, andinclude first interconnects 3 a and second interconnects 3 b. In FIG. 1,the first and second interconnects 3 a and 3 b are alternately disposedalong the direction X.

Each first interconnect 3 a has a first side surface S₁ which is almostparallel to the direction Z, and a second side surface S₂ which ispositioned on the opposite side of the first side surface S₁ andinclines more than the first side surface S₁. Each second interconnect 3b has a third side surface S₃ which is almost parallel to the directionZ, and a fourth side surface S₄ which is positioned on the opposite sideof the third side surface S₃ and inclines more than the third sidesurface S₃. As shown in FIG. 1, the first side surface S₁ of each firstinterconnect 3 a faces the third side surface S₃ of a secondinterconnect 3 b which is adjacent in a positive X direction. The secondside surface S₂ of each first interconnect 3 a faces the fourth sidesurface S₄ of a second interconnect 3 b which is adjacent in a negativeX direction.

Examples of a material of the sidewall interconnects 3 include anelemental substance of metal such as Ti, Ni, Co, W, Mo, Ru, Ta and Al,an alloy containing one or more kinds of those metallic elements, and ametallic compound containing one or more kinds of those metallicelements (e.g., TiN). Other examples of the sidewall interconnects 3include a silicide layer containing substances such as Ti, Ni, Co and W,and a polysilicon layer doped with impurities such as boron, phosphorusand arsenic.

Reference sign Ra shown in FIG. 1 represents first regions between thefirst and third side surfaces S₁ and S₃, and reference sign Rbrepresents second regions between the second and fourth side surfaces S₂and S₄.

The second insulators 4 are formed in the first regions Ra without beingformed in the second regions Rb. Therefore, every two regions betweenthe sidewall interconnects 3 includes one second insulator 4. Eachsecond insulator 4 is disposed in a bottom portion of a first region Raso that the second insulator 4 is partially in contact with the firstand third side surfaces S₁ and S₃. In other words, each second insulator4 is disposed in the bottom portion of the first region Ra without beingdisposed in a top portion of the first region Ra. Examples of the secondinsulators 4 include silicon nitride layers, silicon oxide layers,silicon oxycarbide layers and the like.

The air gaps 5 are formed in the first and second regions Ra and Rb.Hereinafter, the air gaps 5 in the first regions Ra are referred to asfirst air gaps 5 a, and the air gaps 5 in the second regions Rb arereferred to as second air gaps 5 b.

The third insulator 6 is formed on the sidewall interconnects 3, andincludes the first and second air gaps 5 a and 5 b in the first andsecond regions Ra and Rb, respectively. The third insulator 6 is, forexample, an inter layer dielectric. The third insulator 6 may be formeddirectly on the sidewall interconnects 3, or may be formed on thesidewall interconnects 3 via another layer (e.g., sidewall protectionlayer). In this embodiment, a material of the third insulator 6 is aninsulating material with poor embeddability.

(1) Advantages of Second Insulators 4

As described above, the second insulators 4 in the present embodimentare disposed in the first regions Ra without being disposed in thesecond regions Rb. In addition, the second insulators 4 in the presentembodiment are disposed in the bottom portions of the first regions Rawithout being disposed in the top portions of the first regions Ra. Sucha structure provides following advantages.

Firstly, since each second insulator 4 is disposed between a sidesurface S₁ of a first interconnect 3 a and a third side surface S₃ of asecond interconnect 3 b, it becomes possible to prevent thoseinterconnects 3 a and 3 b from falling to the first region Ra side. Inother words, the second insulator 4 can function as a layer to preventthe falling of the interconnects 3 a and 3 b.

Secondly, the following advantage is realized by disposing the secondinsulators 4 not in the entire first regions Ra but only in the bottomportions of the first regions Ra. If the second insulators 4 aredisposed in the entire first regions Ra, the falling of theinterconnects 3 a and 3 b can be prevented, but an insulator with a lowpermittivity or air gaps cannot be formed in the first regions Ra.However, since the second insulators 4 in the present embodiment isdisposed only in the bottom portions of the first regions Ra, theinsulator with the low permittivity or the air gaps can be formed on thesecond insulators 4 in the first regions Ra as well as in the secondregions Rb with preventing the falling of the interconnects 3 a and 3 b.Therefore, according to the present embodiment, capacitances between thesidewall interconnects 3 can be reduced with preventing the falling ofthe sidewall interconnects 3.

Thirdly, since the second insulators 4 are disposed only in the bottomportions of the first regions Ra, the capacitances between the sidewallinterconnects 3 can be controlled uniformly by adjusting the materialand thickness of the second insulators 4. Hereinafter, this thirdadvantage will be described in detail.

As shown in FIG. 1, the first and second interconnects 3 a and 3 b aredifferent in shape. More specifically, they are almostmirror-symmetrical in shape to each other. Therefore, the capacitancebetween the first and third side surfaces S₁ and S₃ is generallydifferent from the capacitance between the second and fourth sidesurfaces S₂ and S₄ even when distances and materials between thosesurfaces are identical. In addition, if the first and second air gaps 5a and 5 b are respectively formed in the first and second regions Ra andRb without disposing the second insulators 4, the size of the first airgaps 5 a becomes larger than the size of the second air gaps 5 b. Thisalso influences the difference in the capacitances between the sidewallinterconnects 3.

On the other hand, a resistance of the first interconnects 3 a is almostidentical to a resistance of the second interconnects 3 b since thoseinterconnects 3 a and 3 b are almost mirror-symmetrical in shape to eachother. In general, it is preferable that the interconnect resistancesand the capacitances between the sidewall interconnects 3 are uniform inan interconnect region.

Accordingly, in the present embodiment, the structure of the insulatorsor the size of the first air gaps 5 a in the first regions Ra areadjusted by adjusting the material and thickness of the secondinsulators 4. Therefore, in the present embodiment, the capacitancesbetween the sidewall interconnects 3 can be adjusted in response to theinterconnect shape, the distance between the sidewall interconnects 3,the material between the sidewall interconnects 3 and the like. Thismakes it possible to uniformly control the capacitances between thesidewall interconnects 3 in the interconnect region. FIG. 1 shows thefirst and second air gaps 5 a and 5 b adjusted to have approximately thesame size.

In the present embodiment, structures shown in FIGS. 2 and 3 may also beapplied. FIGS. 2 and 3 are cross sectional views showing the structuresof semiconductor devices of modifications of the first embodiment.

In FIG. 2, each sidewall interconnect 3 includes a barrier metal layer 3₁ exposed to the first side surface S₁ or the third side surface S₃ andto its bottom surface, and an interconnect material 3 ₂ formed on thebarrier metal layer 3 ₁. The sidewall interconnect 3 with such astructure can be formed by sequentially forming the barrier metal layer3 ₁ and the interconnect material 3 ₂ on the side surface of alater-described core material.

In FIG. 3, the side surfaces S₁ to S₄ of the sidewall interconnects 3are coated with a sidewall protection layer 7 for protecting thesidewall interconnects 3 from oxidization and the like. The sidewallprotection layer 7 is, for example, a silicon nitride layer or a siliconoxide layer. The thickness of the sidewall protection layer 7 is, forexample, 10 nm or less. The sidewall protection layer 7 of FIG. 3 can beformed by forming an insulator to be the sidewall protection layer 7 onthe entire surface of the semiconductor substrate 1, after the removalof a later-described sacrificial layer.

(2) Sizes of Sidewall Interconnects 3 and Second Insulators 4

The sizes of the sidewall interconnects 3 and the second insulators 4are now described with reference to FIG. 1 again.

Reference sign “W” shown in FIG. 1 denotes a width of the secondinsulators 4. Reference signs “Ta” and “Tb” denote widths (thicknesses)of the first and second interconnects 3 a and 3 b, respectively. In thepresent embodiment, the thicknesses “Ta” and “Tb” of the first andsecond interconnects 3 a and 3 b are set to be, for example, the samevalue as the width “W” of the second insulators 4.

Reference sign “H” denotes a height of the sidewall interconnects 3. Ifthe height “H” is too large, the sidewall interconnects 3 might falldown. If the height “H” is too small, the resistances of the sidewallinterconnects 3 might be too high. Accordingly, in the presentembodiment, the height “H” of the sidewall interconnects 3 is set at,for example, 2 to 10 times the thicknesses “Ta” and “Tb” of the sidewallinterconnects 3.

Reference sign “T” denotes a thickness of the second insulators 4. Ifthe thickness “T” is too small, the sidewall interconnects 3 might falldown. If the thickness “T” is too large, the size of the first air gaps5 a might become too small. Accordingly, in the present embodiment, thethickness “T” of the second insulators 4 is set at, for example, 0.2 to0.5 times the height “H” of the sidewall interconnects 3.

The sizes “W”, “Ta”, “Tb”, “H” and “T” may take values different fromthose in the foregoing examples in response to the materials and shapesof the sidewall interconnects 3 and the second insulators 4 and thelike.

(3) Method of Manufacturing Semiconductor Device

A method of manufacturing the semiconductor device is now described withreference to FIGS. 4A to 6B. FIGS. 4A to 6B are cross sectional viewsshowing the method of manufacturing the semiconductor device of thefirst embodiment.

First, as shown in FIG. 4A, the first insulator 2, the second insulator4 and a sacrificial layer 11 are sequentially formed on thesemiconductor substrate 1. The sacrificial layer 11 may be an insulatoror a layer other than the insulator. However, the material of thesacrificial layer 11 in the present embodiment is different from thematerial of the second insulator 4. Examples of the sacrificial layer 11include a silicon nitride layer, a silicon oxide layer, a siliconoxycarbide layer, a silicon layer, an organic material layer and thelike.

Next, as shown in FIG. 4B, a resist layer 12 is formed on thesacrificial layer 11, and the resist layer 12 is then patterned.Reference signs “W₁” and “W₂” denote an interconnect width and a spacewidth of the resist pattern, respectively. In the present embodiment,those widths “W₁” and “W₂” are set, for example, at 50 nm or less. Inthe present embodiment, the resist layer 12 may be replaced with aninsulating layer such as a hard mask layer processed with an upperresist pattern as a mask.

As shown in FIG. 4C, the sacrificial layer 11 and the second insulator 4are then etched by using the resist layer 12 as a mask. As a result, aplurality of core materials 21 are formed from the sacrificial layer 11and the second insulator 4.

As shown in FIG. 5A, the core materials 21 are then slimmed by wetetching or the like so that the width of the core materials 21 isreduced by half. When the sacrificial layer 11 is an Si layer, a mixedaqueous solution of HF and HNO₃ is used as a wet etching solution forslimming the sacrificial layer 11, for example. When the sacrificiallayer 11 is an SiN layer, an H₃PO₄ aqueous solution is used as the wetetching solution, for example. When the sacrificial layer 11 is an SiO₂or SiOC layer, an HF aqueous solution or a mixed aqueous solution of HFand NH₄F is used as the wet etching solution, for example. This alsoapplies to the slimming of the second insulator 4.

As shown in FIG. 5B, an interconnect material 3 to be the sidewallinterconnects is then formed on the entire surface of the semiconductorsubstrate 1. As a result, the interconnect material 3 is formed on sideand upper surfaces of the core materials 21. When forming theinterconnect material 3, it is preferable to apply a method and acondition which promote the formation of the interconnect material 3 onthe side surfaces of the core materials 21. For example, when theinterconnect material 3 is formed by physical vapor deposition (PVD), itis preferable to adjust a bias voltage so that the interconnect material3 is formed on the side surfaces of the core materials 21.

As shown in FIG. 5C, the interconnect material 3 is then etched so thatthe interconnect material 3 remains only on the side surfaces of thecore materials 21. As a result, the sidewall interconnects 3 are formedon the side surfaces of the core materials 21. More specifically, thefirst and second interconnects 3 a and 3 b are formed on the sidesurfaces of each core material 21. The side surfaces of the sidewallinterconnects 3 which are in contact with the core materials 21correspond to the first and third side surfaces S₁ and S₃ of FIG. 1, andthe side surfaces of the interconnects opposite to those side surfacescorrespond to the second and forth side surface S₂ and S₄ of FIG. 1.

As shown in FIG. 6A, the sacrificial layers 11 included in the corematerials 21 are then removed by wet etching or the like. In this case,the sacrificial layers 11 are removed so that the second insulators 4remain. The second insulators 4 may remain in its entirety or in part.When the sacrificial layers 11 are Si, SiN, SiO₂ or SiOC layers, thesame solution as that for the slimming is used as a wet etchingsolution, for example. When the sacrificial layers 11 are organicmaterial layers, the sacrificial layers 11 may be removed by ashing, forexample.

In the present embodiment, the sidewall protection layer 7 of FIG. 3 maybe formed on the entire surface of the semiconductor substrate 1 afterthe step of FIG. 6A.

As shown in FIG. 6B, the third insulator 6 is then formed on the entiresurface of the semiconductor substrate 1. As a result, the sidewallinterconnects 3 are coated with the third insulator 6, and the first andsecond air gaps 5 a and 5 b are formed in the first and second regionsRa and Rb, respectively.

In this way, the semiconductor device of FIG. 1 is manufactured.

The material of the second insulator 4 may be different from thematerial of the first insulator 2, or may be identical to the materialof the first insulator 2. In the former case, the timing to stop theetching of the second insulator 4 in the step of FIG. 4C is controlledby using the etching selectivity of the first and second insulators 2and 4. In the latter case, the timing to stop the etching of the secondinsulator 4 in the step of FIG. 4C is controlled based on etching time.

The material of the third insulator 6 may be different from thematerials of the first and second insulators 2 and 4, or may beidentical to the materials of the first and second insulators 2 and 4.Each of the first to third insulators 2, 4 and 6 may be a single-layerfilm which is made of a single insulating material, or may be amultilayer film formed by stacking plural insulating materials.

(4) Modification of Method of Manufacturing Semiconductor Device

A modification of the method of manufacturing the semiconductor deviceis now described with reference to FIGS. 7A and 7B. FIGS. 7A and 7B arecross sectional views showing the method of manufacturing thesemiconductor device of the modification of the first embodiment.

In the present modification, only the first and second insulators 2 and4 are formed on the semiconductor substrate 1 in the step of FIG. 4A.The steps of FIGS. 4B to 5C are then performed. As a result, as shown inFIG. 7A, the sidewall interconnects 3 are formed on the side surfaces ofthe core materials 21 which is formed only with the second insulators 4.

As shown in FIG. 7B, the second insulators 4 are then partially removedby wet etching or the like. As a result, the interconnect structuresimilar to that of FIG. 6A is achieved. The timing to stop the etchingof the second insulators 4 is controlled based on etching time.

The step of FIG. 6B is then performed. In this way, the semiconductordevice of FIG. 1 can also be manufactured in the present modification.

(5) Effects of First Embodiment

Finally, the effects of the first embodiment will be described.

As described above, the second insulators 4 in the present embodimentare disposed in the first regions Ra without being disposed in thesecond regions Rb. In addition, the second insulators 4 in the presentembodiment are disposed in the bottom portions of the first regions Rawithout being disposed in the top portions of the first regions Ra.

Therefore, according to the present embodiment, it becomes possible toreduce the capacitances between the sidewall interconnects 3 whilepreventing the falling of the sidewall interconnects 3. The secondinsulators 4 can prevent not only the falling of the sidewallinterconnects 3 in the step of FIG. 6A but also the falling of thesidewall interconnects 3 in the steps subsequent to the step of FIG. 6A.

Second Embodiment

FIG. 8 is a cross sectional view showing a structure of a semiconductordevice of a second embodiment.

In the present embodiment, each of the second insulators 4 protrudes tolower portions of the first and second interconnects 3 a and 3 b. As aresult, the width “W” of the second insulators 4 is set to be largerthan a distance “D” between the first and third side surfaces S₁ and S₃above the second insulators 4.

Such a structure can be achieved by making a slimming amount of thesecond insulators 4 smaller than the slimming amount of the sacrificiallayers 11 in the step of FIG. 5A. The slimming amounts can be controlledby adjusting the concentration of the solution and the slimming time.Through the step of FIG. 5A, the width of the second insulators 4becomes larger than the width of the sacrificial layers 11.

According to the present embodiment, contact areas between the secondinsulators 4 and the sidewall interconnects 3 increase, so that it ispossible to prevent the falling of the sidewall interconnects 3 moreeffectively.

If the width “W” of the second insulators 4 is too large, theresistances of the sidewall interconnects 3 may become too high.Accordingly, when “D” is equal to 1 and “Ta+W+Tb” is equal to 3, it ispreferred that the value of “W” is set at 1 to 2 (therefore, “Ta” and“Tb” shown in FIG. 8 take values of 0.5 to 1) in the present embodiment.However, the sizes “W”, “Ta” and “Tb” may take values different fromthose in this example in response to the materials and the shapes of thesidewall interconnects 3 and the second insulators 4.

FIG. 9 is a cross sectional view showing a structure of a semiconductordevice of a modification of the second embodiment.

In FIG. 9, each second insulator 4 protrudes to the lower portions ofthe first and second interconnects 3 a and 3 b in the same way as inFIG. 8. However, the side surfaces of the second insulators 4 in FIG. 9have taper shapes. Such a structure can be achieved by slimming thesecond insulators 4 so that the side surfaces of the second insulators 4have the taper shapes in the step of FIG. 5A. In the presentmodification, contact areas between the second insulators 4 and thesidewall interconnects 3 increase, so that it is possible to prevent thefalling of the sidewall interconnects 3 more effectively.

As described above, each second insulator 4 in the present embodimentprotrudes to the lower portions of the first and second interconnects 3a and 3 b. Therefore, according to the present embodiment, it becomespossible to effectively prevent the falling of the sidewallinterconnects 3 as compared with the first embodiment.

Third Embodiment

FIG. 10 is a cross sectional view showing a structure of a semiconductordevice of a third embodiment.

In the present embodiment, the first and second interconnects 3 a and 3b protrude to bottom portions of trenches between those interconnects 3a and 3 b. As a result, the width “W” of the second insulators 4 is setto be smaller than the distance “D” between the first and third sidesurfaces S₁ and S₃ above the second insulators 4.

Such a structure can be achieved by making the slimming amount of thesecond insulators 4 larger than the slimming amount of the sacrificiallayers 11 in the step of FIG. 5A. Through the step of FIG. 5A, the widthof the second insulators 4 becomes smaller than the width of thesacrificial layers 11.

According to the present embodiment, the cross sections of the sidewallinterconnects 3 increase, so that it is possible to reduce theresistances of the sidewall interconnects 3.

If the width “W” of the second insulators 4 is too small, the first andsecond interconnects 3 a and 3 b may be short-circuited. Accordingly,when “D” is equal to 1 and “Ta+W+Tb” is equal to 3, it is preferred thatthe value of “W” is set at 0.5 to 1 (therefore, “Ta” and “Tb” shown inFIG. 10 take values of 1 to 1.25) in the present embodiment. However,the sizes “W”, “Ta” and “Tb” may take values different from those inthis example in response to the materials and the shapes of the sidewallinterconnects 3 and the second insulators 4.

FIG. 11 is a cross sectional view showing a structure of a semiconductordevice of a modification of the third embodiment.

In FIG. 11, the first and second interconnects 3 a and 3 b protrude tothe bottom portions of the trenches between those interconnects 3 a and3 b in the same way as in FIG. 10. However, the side surfaces of thesecond insulators 4 in FIG. 11 have taper shapes. Such a structure canbe achieved by slimming the second insulators 4 so that the sidesurfaces of the second insulators 4 have the taper shapes in the step ofFIG. 5A. In the present modification, the cross sections of the sidewallinterconnects 3 increase, so that it is possible to reduce theresistances of the sidewall interconnects 3.

As described above, the first and second interconnects 3 a and 3 b inthe present embodiment protrude to the bottom portions of the trenchesbetween those interconnects 3 a and 3 b. Therefore, according to thepresent embodiment, it becomes possible to reduce the resistances of thesidewall interconnects 3 as compared with the first embodiment.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel devices and methods describedherein may be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the devices andmethods described herein may be made without departing from the spiritof the inventions. The accompanying claims and their equivalents areintended to cover such forms or modifications as would fall within thescope and spirit of the inventions.

1. A semiconductor device comprising: a semiconductor substrate; a firstinsulator disposed on the semiconductor substrate; a plurality of firstinterconnects disposed on the first insulator, each first interconnecthaving a first side surface, and a second side surface inclining morethan the first side surface; a plurality of second interconnectsdisposed on the first insulator alternately with the plurality of firstinterconnects, each second interconnect having a third side surfacefacing the first side surface, and a fourth side surface facing thesecond side surface and inclining more than the third side surface; anda second insulator disposed in a first region which is between the firstand third side surfaces without being disposed in a second region whichis between the second and fourth side surfaces, the second insulatorbeing disposed in a bottom portion of the first region so that thesecond insulator is partially in contact with the first and third sidesurfaces.
 2. The device of claim 1, further comprising a third insulatordisposed on the first and second interconnects to include air gaps inthe first and second regions.
 3. The device of claim 2, furthercomprising a protection layer disposed between the second and thirdinsulators, the protection layer being disposed on the first to fourthsurfaces of the first and second interconnects.
 4. The device of claim1, wherein each first interconnect comprises a first barrier metal layerexposed to the first side surface and a bottom surface of the firstinterconnect, and a first interconnect material disposed on the firstbarrier metal layer, and each second interconnect comprises a secondbarrier metal layer exposed to the third side surface and a bottomsurface of the second interconnect, and a second interconnect materialdisposed on the second barrier metal layer.
 5. The device of claim 1,wherein a height of the first and second interconnects is twice to tentimes widths of the first and second interconnects.
 6. The device ofclaim 1, wherein a thickness of the second insulator is 0.2 to 0.5 timesa height of the first and second interconnects.
 7. The device of claim1, wherein a width of the second insulator is larger or smaller than adistance between the first and third side surfaces above the secondinsulator.
 8. The device of claim 7, wherein the width of the secondinsulator and the distance between the first and third side surfacessuffice 0.5D≦W<D or D<W≦2D where W and D denote the width of the secondinsulator and the distance between the first and third side surfaces,respectively.
 9. The device of claim 7, wherein the second insulator hastaper shaped side surfaces.